An integrated memory, for instance, DRAM (Dynamic Random Access Memory), generally has a memory cell array including word lines and bit lines. The memory cells, respectively, being arranged at crossover points of the word lines and bit lines. The memory cells which are usually used in integrated dynamic random access memories generally have a memory cell capacitance and a selection transistor. The memory cell capacitances are, respectively connected via the associated selection transistor of the respective memory cell to one of the bit lines via which a data signal is read out or written in. The control input of the selection transistor is connected to one of the word lines.
During a memory access, a word line is first activated. As a result, the memory cells arranged along a word line are respectively connected up conductively to a bit line via the relevant selection transistor. In this case, the stored charge is divided up in accordance with the memory cell capacitance and bit line capacitance. In accordance with the ratio of these two capacitances, i.e., a transfer ratio, this leads to deflection of the bit line voltage. The read/write amplifier situated at one end of the bit line compares this voltage with the constant voltage on an associated complementary bit line and amplifies the relatively low potential difference between the bit line and the complementary bit line until the bit line has reached the full signal level for a stored logic 1 (corresponding, for example, to a positive supply potential) or the signal level for a logic 0 (corresponding, for example, to a reference potential). At the same time, the inverse signal levels are reached on the associated complementary bit line. A corresponding voltage generator circuit applies a supply voltage to the read/write amplifier for the assessment and amplification operation described in order to set the full signal level.
After the memory cell array has been accessed, the previously selected word lines are deactivated. The bit lines are subsequently put as quickly as possible into a precharge state, proceeding from which a new memory access may be effected. To this end, for each bit line pair, the respective bit line and associated complementary bit line are short-circuited via a precharge circuit and are additionally connected in a high-impedance manner to a precharge voltage of the memory. In order to precharge the bit lines, provision is generally made of a precharge circuit having an associated voltage generator circuit for generating the precharge voltage, which is usually situated at the edge of the memory cell array in the vicinity of the assigned read/write amplifier.
The sensitivity of a read/write amplifier essentially depends on the threshold voltage of the transistors used in the read/write amplifier and on its operating point proceeding from the precharge voltage. In particular, the threshold voltage of CMOS transistors used in the read/write amplifier increases as the memory temperature falls. As the threshold voltage of the transistors in the read/write amplifier increases, correspondingly higher input signal levels for feeding into the read/write amplifier are required for compensation in order to be able to carry out an assessment and amplification operation which is still reliable. On the other hand, when the operating point of the read/write amplifier is higher, the sensitivity of the read/amplifier increases as a result of the precharge voltage being raised.
For example, in a circuit arrangement and a method for setting a bit line precharge voltage in an integrated memory. The bit line precharge voltage is generated by a voltage generator circuit, which is driven by a temperature detector in order to set the precharge voltage in a manner dependent on a memory temperature. The bit line precharge voltage is varied relative to the supply voltage applied to a read/write amplifier during an assessment and amplification operation. When the memory temperature is relatively high, the data retention time for a stored logic 1 is to be improved by reducing the precharge voltage. Setting the precharge voltage relative to the supply voltage of the read/write amplifier can, in practice, give rise to problems since it is necessary to “fight against” the relationship between the precharge voltage and supply voltage (magnitude of the precharge voltage corresponds to half the magnitude of the supply voltage). The relationship naturally arises on account of charge equalization, with the result that the power loss of the memory increases.